Timing and Control Unit
Control Unit
Control unit (CU) of a processor translates from machine instructions to the control signals for the microoperations that implement them.
The block diagram of a hardwired control unit is shown below. It consists of two decoders, a sequence counter, and a number of control logic gates.
Fig: Control unit of a basic computer
Mechanism:
- An instruction read from memory is placed in the instruction resister (IR) where it is decoded into three parts: I bit, operation code and bits 0 through 11.
- The operation code bit is decoded with 3 x 8 decoder producing 8 outputs D0 through D7.
- Bit 15 of the instruction is transferred to a flip-flop I.
- And operand bits are applied to control logic gates.
- The 16 outputs of 4-bit sequence counter (SC) are decoded into 16 timing signals T0 through T15.
This means instruction cycle of basic computer cannot take more than 16.
Timing Signals
- Generated by 4-bit sequence counter and 4x16 decoder.
- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1 . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active: D3T4: SC <¬ 0
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