Timing Diagram for Op-code Fetch Machine Cycle

Fig: Timing Diagram for Op-code Fetch Machine Cycle

The op-code fetch timing diagram can be explained as below:

• The MP places the 16-bit memory address from the program counter on address bus. At time period T1, the higher order memory address is placed on the address lines A15 – A8. When ALE is high, the lower address is placed on the bus AD7 – AD0. The status signal IO/M(bar) goes low indicating the memory operation and two status signals S1 = 1, S0 = 1 to indicate op-code fetch operation.
• At time period T2, the MP sends RD(bar) control line to enable the memory read. When memory is enabled with RD(bar) signal, the op-code value from the addressed memory location is placed on the data bus with ALE low.
• The op-code value is reached at processor register during T3 time period. When data (op-code value) is arrived, the RD(bar) signal goes high. It causes the bus to go into high impedance state.
• The op-code byte is placed in instruction decoder of MP and the op-code is decoded and executed. This happens during time period T4.