Instruction Cycle
- Processing required for complete execution of an instruction is called instruction cycle.
- In Basic Computer, a machine instruction is executed in the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction
Upon the completion of step 4, control goes back to step 1 to fetch, decode and execute the next instruction. This process is continued indefinitely until HALT instruction is encountered.
Fetch and Decode
- Sequence of steps required for fetching instruction from memory to CPU internal register is known as fetch cycle.
- For fetching and decoding, the steps are:
i) Initially, PC holds the address of next instruction to fetch. With timing signal T0, address pointed by PC is transferred to the AR.
ii) The processor fetches instruction to IR from memory location referenced by AR and increment PC for next instruction. This happens with timing signal T1.
iii) Processor interprets instruction and performs required action i.e. decoding during time period T2.
Fig: Flowchart of Instruction Cycle
- Then, among decoded, D7 determines which type of instruction.
i) If D7 = 1, it will be either register-reference or input-output instruction.
a) If I = 1, input-output instruction is executed during T3.
b) If I = 0, register-reference instruction is executed during T3.
ii) If D7 = 0, it will be memory-reference instruction.
a) If I = 1, indirect addressing mode instruction during T3.
b) If I = 0, direct addressing mode instruction during T3.
- The SC is reset after executing each instruction.
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