VHDL is one of the two standard HDLs that are supported by IEEE. Another one is Verilog.
VHDL stands for
V: VHSIC (very high speed integrated circuit)
H: Hardware
D: Description
L: Language
For half adder, let a and b are two input signals, sum and carry are two outputs.
VHDL code:
LIBRARY IEEE;
USE IEEE.std_logic_1164.all; -- use library_name.package_name.package_parts;
ENTITY half_adder IS
PORT (a, b: IN BIT; -- port_name: signal_mode signal_type;
sum, carry: OUT BIT); -- IN, OUT, INOUT, BUFFER
END half_adder;
ARCHITECTURE out_data OF half_adder IS
BEGIN
sum <= a XOR b; -- sum = a⊕b
carry <= a AND b; -- carry = a.b
END out_data;