SAP-2 Architecture

Fig: Architecture of SAP-2 Microprocessor/Computer
  • Hexadecimal Keyboard Encoder: The hexadecimal keyboard encoder receives the data from outer environment and converts it into hexadecimal form. The system can understand and send them to the input port.
  • Input Ports: The SAP-2 contains two input ports which input the data in the system in the most convenient way.
  • PC: PC is the program counter that holds the address of the next instruction to be fetched. It initializes from 0000H to 1111H during the execution.
  • MAR: MAR is the memory address register that stores the complete format of the address sent by the program counter. It stores the final address of the memory word that needs some computations.
  • 64K Memory: It contains 64 K memory where data and instruction reside. All the computations are performed relative to the memory.
  • MDR: MDR is the Memory Data Register which stores the data or operand that is fetched from the memory which is needed for computation.
  • IR: The IR is the Instruction Register that holds the complete format of the Instruction that is to be executed.
  • Control Sequencer: It provides necessary timing signals like T0, T1, T2, ….. and control signals providing the direction for executing the program.
  • Accumulator: The result of all the mathematical operations is stored in accumulator. It is one of the operand of ADD, OUT, SUB instruction. It is also known as processor register.
  • ALU and Flag: The ALU perform all the arithmetic and logical calculations. The flag reflect the intermediate changes on the values during execution.
  • Temporary register, B, C: They are the second operand of the mathematical operations. The register B and C is accessible to the programmer.
  • Output Ports: It consists of two output ports to show the result of OUT instruction.
  • Hexadecimal Display: Unlike Sap-1 which has binary display, Sap-2 has a hexadecimal display to show outputs in the LEDs.

1 comment: