Features of SAP-2 Architecture

• Jump Instructions: loadable PC
• 16-bit program counter
• 8-bit op-code, 42 instructions
• 2 input ports, 2 output ports
• 2K ROM, up to 62K RAM (16-bit addresses) with read and write
• Memory data register (MDR) buffers reads and writes
• Accumulator can write to bus
• Temporary, B and C registers
• 16 arithmetic and logic operations in ALU
• Sign and zero flag 

Bidirectional registers

• connect the inputs to the outputs
• load and enable never simultaneously active
• on load, outputs are 3-state, input is taken from the bus
• on enable, inputs are ignored, output goes to the bus
• 1/2 as many pins
• 1/2 as much bus capacitance 

Flags 

• 2 flip flops, sign flag and zero flag
• set during arithmetic and logic operations to reflect final accumulator contents
• JM jumps only if the sign flag is set (minus result)
• JZ jumps only if the zero flag is set (zero result)
• JNZ jumps if the zero flag is clear (non-zero result) 

Q. What is the value of the sign bit if the accumulator contents are zero?

• In-Class Exercise
• work in groups of up to 3
• design a circuit to implement the flags
• inputs are: 8 bits from the accumulator, clock (use the positive-going edge), 1 LF control line (active high)
• outputs are the flags: ZF, SF 

Fig: Setting the flags