Fetch & Execute Operation: Timing Diagram

• The graphical representation of status of various signals involved during a machine cycle with respect to time is called timing diagram.
• This gives basic idea of what is happening in the system when the instruction is getting fetched and executed, at what instant which signal is getting activated.
• The signals involved during machine cycle are CLK, A15 – A8, AD7 – AD0, IO/M(bar), RD(bar), WR(bar) and S1, S0.

IO/M(bar)	S1	S0	Operation
0	0	0	Halt
0	0	1	Memory write
0	1	0	Memory read
0	1	1	Op-code fetch
1	0	1	IO write
1	1	0	IO read
1	1	1	Interrupt acknowledge