SAP-1 instruction set consists of following instructions
The instruction format of SAP-1 Computer is
(XXXX) (XXXX)
The first four bits make the op-code while the last four bits make the operand (address).
Machine cycle and Instruction cycle
SAP1 has six T-states (three fetch and three execute cycles) reserved for each instruction. Not all instructions require all the six T-states for execution. The unused T- state is marked as No Operation (NOP) cycle. Each T-state is called a machine cycle for SAP1. A ring counter is used to generate a T-state at every falling edge of clock pulse. The ring counter output is reset after the 6th T-state.
FETCH CYCLE – T1, T2, T3 machine cycle
EXECUTE CYCLE - T4, T5, T6 machine cycle
- Complete code includes opcode and operand
- One instruction is executed in one instruction cycle
- Instruction cycle may consist of many machine cycles
- For SAP-1, Instruction cycle = Machine cycle
- Instruction cycle = Fetch cycle + Execution cycle
- Fetch cycle is generally same for all instructions
- Complete code includes opcode and operand
- Like LDA 04H 0000 0100
- One instruction is executed in one instruction cycle
Fig: Instruction Cycle
Fetch and Execution Cycle of SAP-1 instructions
- SAP-1 instruction cycle: 3 clock cycles to fetch and decode phase, 3 clock cycles to execute
- The first three states are:
1. address
2. increment
3. memory
- Controller has a 6-bit ring counter which continuously cycles from 000001 up to 100000 then resets (must be set to 000001 when we initialize the computer)
- Ring counter is clocked on clock high-to-low transition, most of the other circuits in the computer on clock low-to-high transition
Fetch Cycle
- Address state: enable PC to bus three-state output, MAR load line
- Increment state: enable PC increment (and perhaps wait for memory access time)
- Memory state: enable memory CE, IR load line
- IR is loaded on the low-to-high clock transition, so stabilizes before state 4 is entered
t1: MAR ← PC
t2: PC ← PC +1
t3: IR ← RAM
Execution Cycle -- LDA
- state 4: enable IR to bus three-state output, MAR load line
- state 5: enable memory CE, accumulator load line
- state 6: enable nothing
t4: MAR ← (IR (Address of operand))
t5: Accumulator ← RAM
t6: nothing
Execution Cycle -- ADD
- state 4: enable IR to bus three-state output, MAR load line
- state 5: enable memory CE, register B load line
- state 6: enable add, ALU to bus three-state output, accumulator load line
t4: MAR ← (IR (Address of B))
t5: B ← RAM
t6: Accumulator ← Accumulator + B
Micro program
- each SAP-1 block has some control lines:
o each three-state driver has an enable line which connects the driver to the bus
o the program counter also has a count line which, when high, increments the contents on the next low-to-high clock transition
o all registers have a load line (active low)
o the ALU has a subtract line which is high for subtraction and low for addition
- implementing the SAP-1 instructions means raising and lowering these control lines at the appropriate times
- these 12 control lines are the micro program word
- controller must, on each clock cycle, produce 12 bits
- some of these bits are on-off (e.g. three-state output lines) and have a "default off" state
- some of these bits are A/B (e.g. the add-subtract line) and have a "default don't care"
- some bits are active high, some are active low
Controller Implementation
- How to generate micro words?
- if a bit is only on during one cycle, connect it to the corresponding ring counter bit
- if a bit is only on for an instruction, connect it to that instruction (as decoded by a 4-bit 1-of-16 decoder)
- if a bit is only on for an instruction and a cycle, connect it to the AND of the ring counter bit and the decoder output
- if a bit is on for multiple instruction and/or cycles, work out the truth table and use AND/OR or multiplexers to implement it
- alternative: use a ROM
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