Properties
- Single + 5V Supply
- 4 Vectored Interrupts (One is Non Maskable)
- Serial In/Serial Out Port
- Decimal, Binary, and Double Precision Arithmetic
- Direct Addressing Capability to 64K bytes of memory
The Intel 8085 is a new generation, complete 8-bit parallel central processing unit (CPU). The 8085 uses a multiplexed data bus. The address is split between the 8-bit address bus and the 8-bit data bus.
Fig: 8085 Pin Diagram
X1, X2 (Input)
A crystal (or RC, LC network) is connected at these two points. The frequency is divided into two; therefore to operate a system at 3 MHz, the crystal should have a frequency of 6 MHz.
RESET OUT (Output)
This signal indicates that the microprocessor is being reset. It is also used to reset other devices.
SOD (Output)/ SID (Input)
This signal is used for the transmission of data per bit in and out of the processor.
TRAP (Input)
It is a non-maskable interrupt and has the highest priority of any interrupt.
RST 5.5 / RST 6.5 / RST 7.5 (Inputs)
RESTART interrupts. These are the vector interrupts that transfer the program control to the specific memory locations.
RST 7.5 Highest Priority
RST 6.5
RST 5.5 Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR.
INTR (Input)
INTERRUPT REQUEST. This is used as a general purpose interrupt.
INTA (Output)
INTERRUPT ACKNOWLEDGE; this is used to acknowledge an interrupt.
AD0 -AD 7 (Input / Output- 3state)
Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles.
Vss
Ground Reference.
A8 - A15 (Output -3 State)
Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,
S0, S1 (Output)
These status signal, similar to IO/M, can identify various operations, but they are rarely used in small systems.
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S1
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S0
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0
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0
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HALT
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0
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1
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WRITE
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1
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0
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READ
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1
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1
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FETCH
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S1 can be used as an advanced R/W status.
ALE (Output)
Address Latch Enable: it indicates that the bits on AD7-AD0 act as lower 8-bit address bus (A7-A0) when logic high. If ALE=0, it act as data bus (D7-D0).
WR (Output 3-state)
WRITE; indicates the data on the Data Bus is to be written into the selected memory or I/O location.
RD (Output 3state)
READ; indicates the selected memory or I/O device is to be read and that the Data Bus is available for the data transfer.
IO/M (Output)
This is a status signal used to differentiate between I/O and memory operations. When it is high, it indicates an I/O operation; when it is low, it indicates memory operation. This signal is combined with RD and WR to generate I/O and memory control signal.
READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.
RESET IN (Input)
When this pin goes low, it sets the Program Counter to zero and resets the MP, Interrupt Enable and HLDA flip-flops. None of the other flags or registers (except the instruction register) are affected. The CPU is held in the reset condition as long as Reset is applied.
CLK OUT (Output)
This signal can be used as the system clock for other devices.
HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and acknowledge that request.
HOLD (Input)
This signal indicates that a peripheral such as DMA controller is requesting the use of the address and data buses.
Vcc
+5 volt supply
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