Introduction to 8251A PCI (Programmable Communication Interface)

• The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication.
• It supports the serial transmission of data.
• It is packed in a 28 pin DIP.
• It is also called USART (Universal Synchronous Asynchronous Receiver Transmitter).

Fig: Pin Description

Block Diagram: 

The functional block diagram of 8251A consists of five sections. They are: 

• Read/Write control logic
• Transmitter
• Receiver
• Data bus buffer
• Modem control. 

The functional block diagram is shown in fig:

Fig: Functional block diagram of 8251A PCI

Read/Write control logic: 

• The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.
• It monitors the data flow.
• This section has three registers and they are control register, status register and data buffer.
• The eight parallel lines, D7-D0, connect to the system data bus so that data words and control/status words can be transferred to and from the device.
• The chip select (CS) input is connected to an address decoder so the device is enabled when addressed.
• The signals RD, WR, CS and C/D are used for read/write operations with these three registers.
• It has two internal addresses, a control address which is selected when C/D is high (1), and a data address which is selected when C/D input is low (0).
• When the RESET is high, it forces 8251A into the idle mode.
• The CLK (clock input) is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate. 

Transmitter section: 

• The transmitter section accepts parallel data from CPU and converts them into serial data.
• The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.
• When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.
• If buffer register is empty, then TxRDY goes high.
• If output register is empty then TxEMPTY goes high.
• The clock signal, TxC controls the rate at which the bits are transmitted by the USART.
• The clock frequency can be 1, 16 or 64 times the baud rate. 

Receiver Section: 

• The receiver section accepts serial data and convert them into parallel data.
• The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.
• When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again.
• If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer register, the RxRDY line goes high.
• The clock signal RxC controls the rate at which bits are received by the USART.
• During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.
• During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character. 

MODEM Control: 

• The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.
• This unit takes care of handshake signals for MODEM interface.