8085 Microprocessor :: Machine Control Instructions

i) HLT
Halt and enter wait state. The contents of the registers are unaffected during the HLT state.

ii) NOP

No operation is performed. The instruction is fetched and decoded; however, no operation is executed. The instruction is used to fill in time delays or to delete and insert instructions while troubleshooting.

iii) RIM

Read Interrupt Mask. This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and to read serial data input bit. The instruction loads 8 bits in the accumulator with the following interpretations:

                              D7         D6            D5             D4              D3              D2             D1             D0

SID

I7

I6

I5

IE

7.5

6.5

5.5

D7=serial input data bit

D6, D5, D4=interrupts pending if bit=1

D3=interrupt enable; flip-flop is set if bit=1

D2, D1, D0=interrupt masked if bit=1

e.g. After the execution of instruction RIM, the accumulator contained 49H. Explain

(A):      49H = 0           1          0          0          1          0          0          1

RST 7.5 is pending.

Interrupt enable flip-flop is set.

RST 7.5 and 6.5 are enabled. RST 5.5 masked.

iv) SIM

Set Interrupt Mask. This is a multipurpose instruction and used to implement the 8085 interrupts (RST 7.5, 6.5, and 5.5) and serial data output. 

The instruction interprets the accumulator contents as follows: 

                             D7          D6             D5             D4             D3             D2             D1              D0

SOD

SDE

xxx

R7.5

MSE

M7.5

M6.5

M5.5

D7=serial output data

D6=serial data enable (1=enable and 0=disable)

D4=if 1, reset RST 7.5 flip-flop

D3=if 1, mask set enable

D2, D1, D0=masks interrupts if bits=1

• SOD – Serial Output Data: Bit D7 of the accumulator is latched into the SOD output line and made available to a serial peripheral if bit D6=1. 
• SDE – Serial Data Enable: If this bit = 1, it enables the serial output. To implement serial output, this bit needs to be enabled. 
• XXX – Don’t care. 
• R7.5 – Reset RST 7.5: If this bit = 1, RST 7.5 flip-flop is reset. This is an additional control to reset RST 7.5. 
• MSE – Mask Set Enable: If this bit is high, it enables the functions of bits D2, D1, D0. This is a master control over all the interrupt masking bits. If this bit is low, bits D2, D1, and D0 do not have any effect on the masks. 
• M7.5 – D2 = 0, RST 7.5 is enabled. 

                             = 1, RST 7.5 is masked or disabled. 

• M6.5 – D1 = 0, RST 6.5 is enabled. 

                             = 1, RST 6.5 is masked or disabled. 

• M5.5 – D0 = 0, RST 5.5 is enabled. 

                             = 1, RST 5.5 is masked or disabled.