Basic Computer Organization and Design

Program Interrupt

  • Input and Output interactions with electromechanical peripheral devices require huge processing times compared with CPU processing times
  • I/O (milliseconds) versus CPU (nano/micro-seconds)
  • Interrupts permit other CPU instructions to execute while waiting for I/O to complete
  • The I/O interface, instead of the CPU, monitors the I/O device.
  • When the interface founds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU.
  • Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing.
Scenario3: consider a computer which completes instruction cycle in 1µs. Assume I/O device that can transfer information at the maximum rate of 10 characters/sec. Equivalently, one character every 100000µs. Two instructions are executed when computer checks the flag bit and decides not to transfer information. Which means computer will check the flag 50000 times between each transfer. Computer is wasting time while checking the flag instead of doing some useful processing task.

IEN (Interrupt-enable flip-flop)
  • can be set and cleared by instructions
  • When cleared, the computer cannot be interrupted

Interrupt Cycle

This is a hardware implementation of a branch and save return address operation.

Fig: flowchart of interrupt cycle

Fig: Demonstration of interrupt cycle
  • At the beginning of the instruction cycle, the instruction that is read from memory is in address 1. 
  • At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine 
  • The instruction that returns the control to the original program is "indirect BUN 0" 
Register transfer operations in interrupt cycle
Register Transfer Statements for Interrupt Cycle
    - R F/F ← 1 if IEN (FGI + FGO) T0’T1’T2’ ↔ T0’T1’T2’ (IEN) (FGI + FGO): R ← 1
  • The fetch and decode phases of the instruction cycle must be modified: Replace T0, T1, T2 with R'T0, R'T1, R'T2
  • The interrupt cycle : 
RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0

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